Updated tn45 registers
[avrRegisters] / avrRegisters
1 #!/usr/bin/perl
2
3 # (c) copyright by J.P. Hendrix
4
5 # Script to enrich disassembly output with register and interrupt vector *names*
6 # Use: `make disassemble | ./attinyRegisters.pl`
7
8 use warnings;
9 use strict;
10
11 use Getopt::Long;
12
13 sub help_and_exit {
14         print " --avr=..        AVR type identifier";
15         print "\n";
16         exit;
17 }
18
19 # Get command line arguments
20 my %parameters;
21 GetOptions (\%parameters , 'avr=s' ) || help_and_exit;
22
23 my $avr = $parameters{ 'avr' } || 'tn2313';
24
25 my %name;
26
27 sub checkRegister {
28         my $name = shift;
29         my $addr = shift;
30         if ( $name eq '?' ) { $name = "?_$addr"; }
31         return $name;
32 }
33
34 ###
35 ### Read register names and interrupt vectors into memory
36 ###
37 foreach my $line ( <DATA> ) {
38         chomp( $line );
39         my ( $type , $addr , $tn45 , $tn2313 , $m328 , $m16 , $m1280 ) = split( /[      ]+/ , $line );
40         $name{ $type }->{ $addr }->{ 'tn45' }   = checkRegister( $tn45 , $addr );
41         $name{ $type }->{ $addr }->{ 'tn2313' } = checkRegister( $tn2313 , $addr );
42         $name{ $type }->{ $addr }->{ 'm328' }   = checkRegister( $m328 , $addr );
43         $name{ $type }->{ $addr }->{ 'm16' }    = checkRegister( $m16 , $addr );
44         $name{ $type }->{ $addr }->{ 'm1280' }  = checkRegister( $m1280 , $addr );
45 }
46
47 ###
48 ### Check if command line given AVR is supported
49 ###
50 my $supportedController = 0;
51 foreach my $controller ( keys( %{ $name{ 'REG' }->{ '0x02' } } ) ) {
52         if ( "$controller" eq "$avr" ) {
53                 $supportedController = 1;
54         }
55 }
56 if ( $supportedController == 0 ) { 
57         die "Controller $avr is not supported.\n";
58 }
59
60 foreach my $line ( <STDIN> ) {
61         chomp( $line );
62         
63         # change comments to register names
64         foreach my $address ( keys( $name{ 'REG' } ) ) {
65                 foreach my $mnemonic ( qw( cbi out sbi sbic sbis ) ) {
66                         $line =~ s/($mnemonic\W+)($address)([^;]+;)(.*$)/$1$name{ 'REG' }->{ $address }->{ $avr }$3 $2/;
67                 }
68                 $line =~ s/(in[^,]+, )$address[^;]+;.*$/$1$name{ 'REG' }->{ $address }->{ $avr }\t; $address/;
69         }
70         
71         foreach my $address ( keys( $name{ 'INTVEC' } ) ) {
72                 $line =~ s/<$address([^0-9])/<$name{ 'INTVEC' }->{ $address }->{ $avr }$1/g;
73         }
74         print $line . "\n";
75 }
76
77 __DATA__
78 type    addr            tn45            tn2313                  m328            m16             m1280
79 REG     0x02            ?               UBRRH                   ?               ?               PORTA
80 REG     0x03            ?               UCSRC                   ?               ?               PINB
81 REG     0x09            ?               UBRRL                   ?               ?               PIND
82 REG     0x0a            ?               UCSRB                   DDRB            ?               DDRD
83 REG     0x0b            ?               UCSRA                   PORTB           ?               PORTD
84 REG     0x0c            ?               UDR                     ?               ?               PINE
85 REG     0x0d            USICR           USICR                   ?               ?               DDRE
86 REG     0x0e            USISR           USISR                   ?               ?               PORTE
87 REG     0x0f            USIDR           USIDR                   ?               ?               PINF
88 REG     0x10            ?               PIND                    ?               ?               DDRF
89 REG     0x11            ?               DDRD                    ?               ?               PORTF
90 REG     0x12            ?               PORTD                   ?               ?               PING
91 REG     0x16            PINB            PINB                    ?               ?               TIFR1
92 REG     0x17            DDRB            DDRB                    ?               ?               TIFR2
93 REG     0x18            PORTB           PORTB                   ?               ?               TIFR3
94 REG     0x19            ?               PINA                    ?               PINA            TIFR4
95 REG     0x1a            ?               DDRA                    ?               DDRA            TIFR5
96 REG     0x1b            ?               PORTA                   ?               PORTA           PCIFR
97 REG     0x22            ?               TCCR1C                  ?               ?               EEARH
98 REG     0x24            ?               ICR1L                   ?               ?               TCCR0A
99 REG     0x25            ?               ICR1H                   ?               ?               TCCR0B
100 REG     0x26            ?               CLKPR                   ?               ?               TCNT0
101 REG     0x27            PLLCSR          PLLCSR                  ?               ?               ?
102 REG     0x28            ?               OCR1BL                  ?               ?               OCR0B
103 REG     0x29            OCR0A           OCR1BH                  ?               ?               ?
104 REG     0x2a            TCCR0A          OCR1AL                  ?               ?               GPIOR1
105 REG     0x2b            OCR1B           OCR1AH                  ?               ?               GPIOR2
106 REG     0x2c            GTCCR           TCNT1L                  ?               ?               SPCR
107 REG     0x2d            OCR1C           TCNT1H                  ?               ?               SPSR
108 REG     0x2e            OCR1A           TCCR1B                  ?               ?               SPDR
109 REG     0x2f            TCNT1           TCCR1A                  ?               ?               ?
110 REG     0x30            TCCR1           TCCR1                   ?               ?               ?
111 REG     0x31            OSCCAL          OSCCAL                  ?               ?               ?
112 REG     0x32            TCNT0           TCNT0                   ?               ?               ?
113 REG     0x33            TCCRB0          TCCRB0                  ?               ?               ?
114 REG     0x34            MCUSR           MCUSR                   ?               ?               ?
115 REG     0x35            MCUCR           MCUCR                   ?               ?               MCUCR
116 REG     0x38            TIFR            TIFR                    ?               ?               ?
117 REG     0x3a            GIFR            EIFR                    ?               ?               ?
118 REG     0x3b            GIMSK           GIMSK                   ?               ?               RAMPZ
119 REG     0x3d            SPL             SPL                     SPL             SPL             SPL
120 REG     0x3e            SPH             SPH                     SPH             SPH             SPH
121 REG     0x3f            SREG            SREG                    SREG            SREG            SREG
122 INTVEC  __ctors_end     RESET_vect      RESET_vect              RESET_vect      RESET_vect      RESET_vect
123 INTVEC  __vector_1      INT0_vect       ?                       ?               ?               INT0_vect
124 INTVEC  __vector_2      ?               ?                       ?               ?               INT1_vect
125 INTVEC  __vector_3      ?               TIMER1_CAPT_vect        ?               ?               INT2_vect
126 INTVEC  __vector_4      TIMER1_OVF_vect TIMER1_COMPA_vect       ?               ?               INT3_vect
127 INTVEC  __vector_5      ?               TIMER1_OVF_vect         ?               ?               INT4_vect
128 INTVEC  __vector_6      ?               ?                       ?               ?               INT5_vect
129 INTVEC  __vector_7      ?               USART_RX_vect           ?               ?               INT6_vect
130 INTVEC  __vector_8      ?               USART_UDRE_vect         ?               ?               INT7_vect
131 INTVEC  __vector_9      ?               USART_TX_vect           ?               ?               PCINT0_vect
132 INTVEC  __vector_13     ?               TIMER0_COMPA_vect       ?               ?               TIMER2_COMPA_vect
133 INTVEC  __vector_23     ?               ?                       ?               ?               TIMER0_OVF_vect
134 type    addr            tn45            tn2313                  m328            m16             ?