Initial Version
authorJ. Hendrix <gitweb@localhost>
Thu, 9 May 2013 18:01:09 +0000 (20:01 +0200)
committerJ. Hendrix <gitweb@localhost>
Thu, 9 May 2013 18:01:09 +0000 (20:01 +0200)
avrRegisters [new file with mode: 0755]

diff --git a/avrRegisters b/avrRegisters
new file mode 100755 (executable)
index 0000000..0e85558
--- /dev/null
@@ -0,0 +1,123 @@
+#!/usr/bin/perl
+
+# (c) copyright by J.P. Hendrix
+
+# Script to enrich disassembly output with register and interrupt vector *names*
+# Use: `make disassemble | ./attinyRegisters.pl`
+
+use warnings;
+use strict;
+
+use Getopt::Long;
+
+sub help_and_exit {
+        print "        --avr=..        AVR type identifier";
+       print "\n";
+        exit;
+}
+
+# Get command line arguments
+my %parameters;
+GetOptions (\%parameters , 'avr=s' ) || help_and_exit;
+
+my $avr = $parameters{ 'avr' } || 'tn2313';
+
+my %name;
+
+sub checkRegister {
+       my $name = shift;
+       my $addr = shift;
+       if ( $name eq '?' ) { $name = "?_$addr"; }
+       return $name;
+}
+
+###
+### Read register names and interrupt vectors into memory
+###
+foreach my $line ( <DATA> ) {
+       chomp( $line );
+       my ( $type , $addr , $tn45 , $tn2313 , $m328 ) = split( /[      ]+/ , $line );
+       $name{ $type }->{ $addr }->{ 'tn45' } = checkRegister( $tn45 , $addr );
+       $name{ $type }->{ $addr }->{ 'tn2313' } = checkRegister( $tn2313 , $addr );
+       $name{ $type }->{ $addr }->{ 'm328' } = checkRegister( $m328 , $addr );
+}
+
+###
+### Check if command line given AVR is supported
+###
+my $supportedController = 0;
+foreach my $controller ( keys( %{ $name{ 'REG' }->{ '0x02' } } ) ) {
+       if ( "$controller" eq "$avr" ) {
+               $supportedController = 1;
+       }
+}
+if ( $supportedController == 0 ) { 
+       die "Controller $avr is not supported.\n";
+}
+
+foreach my $line ( <STDIN> ) {
+       chomp( $line );
+       
+       # change comments to register names
+       foreach my $address ( keys( $name{ 'REG' } ) ) {
+               foreach my $mnemonic ( qw( cbi out sbi sbic sbis ) ) {
+                       $line =~ s/($mnemonic\W+)($address)([^;]+;)(.*$)/$1$name{ 'REG' }->{ $address }->{ $avr }$3 $2/;
+               }
+               $line =~ s/(in[^,]+, )$address[^;]+;.*$/$1$name{ 'REG' }->{ $address }->{ $avr }\t; $address/;
+       }
+       
+       foreach my $address ( keys( $name{ 'INTVEC' } ) ) {
+               $line =~ s/<$address([^0-9])/<$name{ 'INTVEC' }->{ $address }->{ $avr }$1/g;
+       }
+       print $line . "\n";
+}
+
+__DATA__
+type   addr            tn45            tn2313                  m328
+REG    0x02            ?               UBRRH                   ?
+REG    0x03            ?               UCSRC                   ?
+REG    0x09            ?               UBRRL                   ?
+REG    0x0a            ?               UCSRB                   DDRB
+REG    0x0b            ?               UCSRA                   PORTB
+REG    0x0c            ?               UDR                     ?
+REG    0x0d            USICR           USICR                   ?
+REG    0x0e            USISR           USISR                   ?
+REG    0x0f            USIDR           USIDR                   ?
+REG    0x10            ?               PIND                    ?
+REG    0x11            ?               DDRD                    ?
+REG    0x12            ?               PORTD                   ?
+REG    0x16            PINB            PINB                    ?
+REG    0x17            DDRB            DDRB                    ?
+REG    0x18            PORTB           PORTB                   ?
+REG    0x19            ?               PINA                    ?
+REG    0x1a            ?               DDRA                    ?
+REG    0x1b            ?               PORTA                   ?
+REG    0x22            ?               TCCR1C                  ?
+REG    0x24            ?               ICR1L                   ?
+REG    0x25            ?               ICR1H                   ?
+REG    0x26            ?               CLKPR                   ?
+REG    0x28            ?               OCR1BL                  ?
+REG    0x29            ?               OCR1BH                  ?
+REG    0x2a            ?               OCR1AL                  ?
+REG    0x2b            ?               OCR1AH                  ?
+REG    0x2c            ?               TCNT1L                  ?
+REG    0x2d            ?               TCNT1H                  ?
+REG    0x2e            ?               TCCR1B                  ?
+REG    0x2f            TCNT1           TCCR1A                  ?
+REG    0x35            MCUCR           MCUCR                   ?
+REG    0x38            TIFR            TIFR                    ?
+REG    0x3a            GIFR            EIFR                    ?
+REG    0x3b            GIMSK           GIMSK                   ?
+REG    0x3d            SPL             SPL                     SPL
+REG    0x3e            SPH             ?                       SPH
+REG    0x3f            SREG            SREG                    SREG
+INTVEC __ctors_end     RESET_vect      RESET_vect              ?
+INTVEC __vector_1      INT0_vect       ?                       ?
+INTVEC __vector_3      ?               TIMER1_CAPT_vect        ?
+INTVEC __vector_4      TIMER1_OVF_vect TIMER1_COMPA_vect       ?
+INTVEC __vector_5      ?               TIMER1_OVF_vect         ?
+INTVEC __vector_7      ?               USART_RX_vect           ?
+INTVEC __vector_8      ?               USART_UDRE_vect         ?
+INTVEC __vector_9      ?               USART_TX_vect           ?
+INTVEC __vector_13     ?               TIMER0_COMPA_vect       ?
+type   addr            tn45            tn2313                  m328